Sound capture (Part 5)

Part 1234, 5

After some new experiments on sound analysis, I used a different design for the microphone amplifying section, that I am happy to share with you (From the statistics of Arduinoos, I know that sound capture is a topic of major interest for many of you).

Here is the schematics that I shall explain in details

The whole circuit is supplied with a clean +5 to +12V, filtered by C5. The microphone (electret type) is biased through R7, R8, using a filtering capacitor C2 for removing some power supply noise. The active pin of the micro phone is connected to the first stage of an inverting amplifier (IC2B) via a decoupling capacitor which stops the DC component of the signal and all the AC component to go through. The gain of this amplifier is set by R3 and R4, with G=R3/R4. The non inverting input of the amplifier is set to a virtual ground at half the value of VCC (typcally 5/2=2.5V), so that the signal at rest is about half VCC and swings around this value. Halving VCC is performed by the divider bridge R1/R2, stabilized by C3 and C4. Lacking to install these capacitors may lead to an unstable output. The output of this stage is available at pin 7 of IC2B. Some applications may require an even higher gain, which is achieved by a second amplifying stage. This second stage uses exactly the same design than for the first stage; its gain is set by R5 and R6 [erratic spot on R6 and GND: do not connect] . It shares the same virtual ground as for the first stage. The total gain of the amplifier is the product of the gains from the two stages.

BTW, why would we use two stages? It is very important not to violate the bandwidth limit of the op amp at the highest frequency seen by the circuit. Practical circuits can include gains of 100, but higher gains could cause the circuit to oscillate unless special care is taken during PC board layout. It is better to cascade two or more equal-gain stages than to attempt high gain in a single stage.

Typical components values:

  • C1=0.1µF
  • C2, C3, C4=2.2µF
  • C5=100µF
  • R6, R7=4.7 kOhm
  • R3, R4, R5, R6= depends on gain which should be constrained to 100 for each stage
  • IC2=Any low noise, single supply, rail to rail operational amplifier


Adding more stages is possible. Applying successive stages of  2^n gains is a valid option for improving the dynamic range of the ADC to which the amplifying stage is connected to.


[Updated schematics: this version contains an improved stabilized biasing circuit in addition to minor corrections]



  1. mymadi says:

    Hi Didier,

    By looking the 2nd circuit for adding more stage, after the R6 you put it to GND, it is true?

    Sorry, if I’m wrong…

  2. Didier says:

    Your are 100% right. No connexion between GND and R6. My mistake

  3. mymadi says:

    I think the first circuit also R6 go to GND.. ;)..

    Anyway, can I know what software do you used for circuit diagram?


  4. mymadi says:

    Hi Didier,

    The update version compatible or not with 5V?

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